1. The Field of the Invention
The present invention relates to methods for doping an active region on a semiconductor substrate by ion implantation and, more specifically, to methods for doping a first active region without simultaneously doping a second exposed active region.
2. The Relevant Technology
Integrated circuits are manufactured by an elaborate process in which a variety of different electronic devices are integrally formed on a small semiconductor wafer. Conventional electronic devices include capacitors, resistors, transistors, diodes, and the like. In advanced manufacturing of integrated circuits, hundreds of thousands of electronic devices are formed on a single chip.
The variety of electronic devices making up an integrated circuit are formed through a series of layering and stripping steps. By selectively combining layers of conductive, nonconductive, and semiconductive material, each of the different electronic devices can be formed.
One additional step used in making different devices is doping. Doping is a process in which ions from a selected material are introduced within a portion of a layer of semiconductive material. Doping allows for selectively modifying the electrical properties of the semiconductive material of a silicon wafer. The dopants may be ion implanted or diffused.
One of the problems with doping by ion implantation is that the areas to be doped are usually extremely small. As a result, it is difficult to isolate an ion stream so that the ions only strike a desired area. One preferred method for doping is to first deposit a layer of insulative material over the semiconductive material. A photolithography step is then used to selectively remove portions of the deposited insulative layer so as to expose only the desired portions of the semiconductive material for doping.
Photolithography is a complex, multiple step process in which a layer of photoresist is deposited over a layer of material on the semiconductor wafer. Typically, the layer of material is an insulative material that overlies a semiconductor substrate. Various wavelengths of light are then exposed to the portion of the photoresist material located over the portion of the layer of insulative material that is desired to be removed. The exposed photoresist can then be removed with a developer agent. Next, the semiconductor wafer is exposed to an etching compound which can be either a gas or liquid. The etching compound etches through the portion of the layer of insulative material that is not protected by the photoresist to expose the underlying semiconductor substrate.
Once the semiconductor substrate has been exposed via the photolithography process, the semiconductor wafer is bombarded with the desired ions. A portion of the ions pass through the openings in the photoresist and insulative layer to implant and thus dope the selected areas of the semiconductor substrate.
At times it is desirable to dope a first and a second area of a semiconductive substrate with different types of ions. In so doing, however, it is necessary in some fashion to cover and protect the second area while the first area is doped and then to cover and protect the first area while the second area is doped. This prevents contamination of the different areas with unintended ion doping. Protecting the area not being doped is typically accomplished through the application of an insulation layer or a layer of photoresist as discussed above. The repeated application and removal of layers of insulation and/or photoresist, however, is both a time consuming and expensive process. This is especially true where numerous doping steps are required in the formation of an integrated circuit.
One process where the problem of doping is easily witnessed is in the formation of a complementary field effect transistor, commonly referred to as a "CMOS" transistor. A CMOS transistor is defined as a transistor having an N-channel MOS transistor and a P-channel MOS transistor on the same semiconductor substrate. During processing, a single polysilicon layer may be used to form both N-channel and P-channel gates. The N-channel devices are formed first, with unetched polysilicon left in the future P-channel regions until N-channel processing is complete. The mask used to subsequently pattern the P-channel devices is also used to blanket and protect the already formed N-channel devices, or vice versa. This process is herein referred to as the split polysilicon CMOS last process which is disclosed in Japanese patent number 57-17164 issued to Masahide Ogawa on Jan. 28, 1982.
Although the split polysilicon CMOS last process has been found an effective way in making transistors, since the gate channel in the P-channel device must be doped with a different dopant than in the N-channel device, numerous masking steps are required to prevent contamination between the two gates.
What is needed is improved methods for doping a semiconductor material by ion implantation. Improved methods are also needed for doping a first active region by ion implantation without doping an exposed second active region. It would be desirable to provide methods for doping a first active region by ion implantation without having to cover the exposed second active region. It would also be desirable to provide methods for doping a first of two exposed active regions in a minimal time as well as at a minimal cost. Additionally, it would be desirable to develop methods for producing a CMOS circuit that eliminates a masking step compared to a conventional split polysilicon P-channel last CMOS process.